Stencils, Solvers, and Sphere Decoders on FPGAs
DescriptionWe review some recent work on designing high performance structured mesh stencil accelerators on FPGA, building on a performance model that helps guide the design space exploration. We then review an accelerator design for tridiagonal system solvers applied to complex applications. For both applications we compare against GPU implementations on an NVIDIA V100, and show significant energy benefits for the FPGA. Finally, we present some recent work on accelerating Sphere Decoding for Massive MIMO on FPGAs.
TimeMonday, 14 November 20223:30pm - 4pm CST