Workshop: Eighth International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2022)
Event TypeWorkshop
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TimeMonday, 14 November 20228:30am - 5pm CST
DescriptionAs conventional von-Neumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency, and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.

Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its eight year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.

Workshop Website
8:30am - 8:35am CSTH2RC – Opening Remarks
8:35am - 9:30am CSTProgramming Methods, Architectures, and Applications of Reconfigurable Technologies in HPC
9:30am - 10:00am CSTEnabling VirtIO Driver Support on FPGAs
10:00am - 10:30am CSTH2RC 2022 – Morning Break
10:30am - 11:00am CSTA First Step Toward Support for MPI Partitioned Communication on SYCL-Programmed FPGAs
11:00am - 11:30am CSTFast and Energy-Efficient Derivatives Risk Analysis: Streaming Option Greeks on Xilinx and Intel FPGAs
11:30am - 12:00pm CSTAccelerating Kernel Ridge Regression with Conjugate Gradient Method for Large-Scale Data Using FPGA High-Level Synthesis
12:00pm - 1:30pm CSTH2RC – Lunch Break
1:30pm - 2:00pm CSTPYNQ for HPC
2:00pm - 2:30pm CSTMLIR Compilers for Heterogeneous Computing
2:30pm - 2:45pm CSTVirtual Screening on FPGA: Performance and Energy versus Effort
2:45pm - 3:00pm CSTH2RC Open Slot
3:00pm - 3:30pm CSTH2RC – Afternoon Break
3:30pm - 4:00pm CSTStencils, Solvers, and Sphere Decoders on FPGAs
4:00pm - 4:30pm CSTSYCL and RISC-V
4:30pm - 4:50pm CSTAMD HACC Program – Overview and Infrastructure at PC2
4:50pm - 5:00pm CSTH2RC – Closing Remarks
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