Workshop: LLVM-HPC2022: The Eighth Workshop on the LLVM Compiler Infrastructure in HPC
Authors: Shalini Jain and S. VenkataKeerthy (Indian Institute of Technology (IIT), Hyderabad); Rohit Aggarwal and Tharun Kumar Dangeti (Advanced Micro Devices (AMD) Inc, India); Dibyendu Das (Intel Labs, India); and Ramakrishna Upadrasta (Indian Institute of Technology (IIT), Hyderabad)
Abstract: We present a Reinforcement Learning (RL) based approach to efficiently perform loop-distribution with the goals of optimizing for vectorization and locality. We generate the SCC Dependence Graph for each loop of the program. Our RL model learns to predict the distribution order of the loop by performing a topological walk of graph. The RL-reward is computed using instruction cost and number of cache misses. For training purposes, we also propose a novel strategy to extend the training set by generating new loops.
We show results on x86 architecture on various benchmarks: TSVC, LLVM-Test-Suite, PolyBench, PolyBenchNN. Our framework achieves an average improvement of 3.63% on TSVC, 4.61% on LLVM-Test-Suite MicroBenchmarks, 1.78% on PolyBench and 1.95% on PolyBenchNN benchmark suites for performance, with LLVM-O3 flag as baseline. We also show the improvements on other performance metrics like Instruction Per Cycle (IPC), Number of loops distributed and vectorized, and L1 cache performance.