Authors: Debendra Das Sharma (Intel Corporation, Peripheral Component Interconnect Special Interest Group (PCI-SIG)), Richard Solomon (Synopsys Inc, Peripheral Component Interconnect Special Interest Group (PCI-SIG))
Abstract: For the past 30 years, PCI-SIG® has delivered specifications that remain ahead of the industry demand for a high-bandwidth, low-latency I/O interconnect. With each new PCI Express® (PCIe®) specification, PCI-SIG has consistently delivered enhanced performance, unprecedented speeds, and low latency. With the release of the PCIe 6.0 specification in 2022, PCI-SIG moved into the PAM4 era, delivering 64 GT/s data rate while maintaining full backwards compatibility. PCI-SIG also introduced official PCIe 5.0 Compliance Testing in 2022. In this session, attendees will learn how PCIe 6.0 architecture enables next-generation HPC applications. Presenters will also highlight PCIe 5.0 technology adoption and applications.
Long Description: PCI-SIG® continues to evolve the PCI Express® (PCIe®) architecture, supporting developers now with PCIe 5.0 compliance testing and enabling companies to plan their roadmaps for future market requirements with PCIe 6.0 and the newly announced PCIe 7.0 specification. This session will detail the PCIe 6.0 specification, provide a brief overview of the PCIe 5.0 Compliance Program and share how the PCI-SIG specifications can meet your system needs at any speed. Released earlier this year, the PCIe 6.0 specification delivers the fastest data rate yet at 64 GT/s (up to 256 GB/s via x16 configuration), doubling the bandwidth of the PCIe 5.0 specification while maintaining full backwards compatibility with previous generations. PCIe 6.0 technology redefines the fabric, adding PAM4 (pulse amplitude modulation) signaling, FLIT-based encoding and low-latency Forward Error Correction (FEC). These new features allow for low latency, minimal complexity and limited bandwidth overhead. PCIe 6.0 technology is a cost-effective and scalable interconnect solution for data-intensive markets including artificial intelligence and machine learning, data center networking, HPC and Internet of Things (IoT). The PCIe 6.0 specification continues to meet industry demand, while adding new features and improvements to maintain high speed and low latency for years to come.
This year also saw the introduction of official PCIe 5.0 Compliance Testing and this session will provide a brief overview of the PCIe 5.0 Compliance Program. PCIe 5.0 architecture is already seeing widespread adoption in SSDs and supports GPUs in AI/ML applications. This interactive session includes brief technical presentations from PCI Express technology experts. In the first presentation, PCI-SIG® Board Member Debendra Das Sharma will provide an overview of the “nuts and bolts” of PCIe 6.0 technology and how PCI-SIG was able to achieve data rates of 64 GT/s without sacrificing signal integrity. He will also introduce PCIe 7.0 specification, which is targeted for release in 2025. In the following presentation, PCI-SIG Vice President Richard Solomon will discuss the various use cases and applications that will be accelerated by PCIe 6.0 technology, provide an update on the PCIe 5.0 compliance program and a look toward the future of PCIe technology. Following each presentation, audience members will have the opportunity to “ask the experts” questions and participate in the discussion. The intention of this session is to facilitate a round table discussion where all points of view are considered. Please note that presenters will not be able to answer questions about individual companies’ plans involving PCIe technology. PCIe technology has experienced massive adoption rates and served as the de facto interconnect of choice for nearly three decades. This session is an excellent opportunity for system developers and engineers interested in learning more about the next-gen features of the PCIe 6.0 specification, PCIe 5.0 compliance testing opportunities and to chat with industry experts in a relaxed setting.
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