I am currently a Principal Member of the Technical Staff at Sandia National Laboratories in New Mexico, USA. My work is centered on improving the capabilities — either through faster execution or through increased computational fidelity and scale — of Sandia’s multi physics engineering application suites and solver libraries. A key theme which runs through this work is optimizing these codes for existing platforms as well as next-generation platforms through to Exascale. The rapid changes in hardware have seen our groups progressively utilize more abstractions that can frustrate compiler optimization passes and hide important optimization opportunities; part of my work investigates why such instances occur and how we can work with leading industry vendors and the open source community to ensure that their developer environments allow us to effectively utilize as much of the hardware as possible. Since 2011, I have also developed architectural simulation models within Sandia’s Structural Simulation Toolkit (SST) for the DOE in areas such as lightweight processor emulation, memory access patterns/traces and, most recently, the Ember collection of scalable communication patterns that represent important characteristics of our application portfolio. This work was utilized by all five of the industry vendors selected for DOE’s DesignForward interconnect research projects because of its unparalleled scale, performance and accuracy. The most recent extension of my duties has included leading the application performance analysis research team at Sandia as we port and optimize codes for Intel’s Knights Landing Xeon Phi architecture and the forthcoming LLNL Sierra machine which will comprise high-performance IBM POWER9 processors with the next- generation NVIDIA Volta GPU. In 2017, I will also join other DOE colleagues as Sandia’s technical lead for the United States Exascale Computing Project Hardware Technology PathForward thrust area.
Chair of Sessions
Exascale Computing
Modeling and Simulation
Performance Portability
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