Fabrizio Petrini is a Principal Engineer of the Intel Parallel Computing Labs in Santa Clara, CA. His research interests include data-intensive algorithms, high performance interconnection networks and novel architectures for graph analytics and sparse linear algebra. He is the Co-Principal investigator of the Intel DARPA HIVE and SDH programs that will deliver the first version of the Programmable Integrated Unified Memory Architecture (PIUMA) in late 2021. Fabrizio has published over 120 peer-reviewed journal and conference articles which received 6000 citations and is serving as associate editor for the IEEE Transactions on Computers. He received a PhD in Computer Science from the University of Pisa, Italy, and was a postdoc at UC Berkeley and a research fellow at the Computing Laboratory of the Oxford University in the UK.