CXL, PMEM, and Checkpointing – The Path Forward
DescriptionWe present nascent work that introduces a path forward for leveraging CXL 2.0 and 3.0 subprotocols, notably the CXL.cache and CXL.mem subprotocols, in a novel fashion. We intend to demonstrate CXL Type 1 and Type 2 device functionality in order to make a strong case for more and larger cache levels. This will not only create a novel memory hierarchy for us to accelerate precomputed (speculated) memory paths but will effectively operate as a live checkpoint and snapshot option since we are moving many traditional RAM operations onto redefined non-volatile media, initially CXL-enabled NVMe drives.
Event Type
TimeMonday, 14 November 202211:50am - 11:55am CST
Registration Categories
Reliability and Resiliency
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