Reinforcement Learning Strategies for Compiler Optimization in High Level Synthesis
DescriptionHigh Level Synthesis (HLS) offers a possible programmability solution for FPGAs but currently delivers far lower hardware quality than circuits written using Hardware Description Languages (HDLs). One reason is because the standard set of code optimizations used by CPU compilers, such as LLVM, are not well suited for an FPGA backend.

While much work has been done employing reinforcement learning for compilers in general, that directed toward HLS is limited and conservative. We expand both the number of learning strategies for HLS compiler tuning and the metrics used to evaluate their impact. Our results show improvements over state-of-art for each standard benchmark evaluated and learning quality metric investigated. Choosing just the right strategy can give an improvement of 23x in learning speed, 4x in performance potential, 3x in speedup over -O3, and has the potential to largely eliminate the fluctuation band from the final results.
Event Type
TimeSunday, 13 November 20229am - 9:30am CST
Registration Categories
Session Formats
Back To Top Button