Leveraging Stencil Computation Performance with Temporal Blocking Using Large Cache Capacity on AMD EPYC 7003 Processors with AMD 3D V-Cache Technology
DescriptionIn structured grid finite-difference, finite-volume, and finite-element discretizations of partial differential equation conservation laws, regular stencil computations constitute the main core kernel in many temporally explicit approaches for such problems. For various blocking dimensions, the Spatial Blocking (SB) approach enables data reuse within multiple cache levels.
Introduced in GIRIH, the Multi-core Wavefront Diamond blocking (MWD) method optimizes practically relevant stencil algorithms by combining the concepts of diamond tiling and multi-core aware wavefront temporal blocking, leading to significant increase in data reuse and locality.
We evaluate the performance of MWD on a variety of recent multi-core architectures. Among all of them, the new AMD multi-processor, codenamed Milan-X, provides an unprecedented capacity for the Last Level Cache. We show that the Milan-X hardware design is ideal for the MWD method, and significant performance gain can be achieved relative to its predecessors Milan and Rome.
TimeTuesday, 15 November 20228:30am - 5pm CST