Debris Pose Estimation Using Deep Learning on FPGA
SessionResearch Posters Display
DescriptionIt is difficult to implement a CNN for edge processing in satellites, automobiles, and more, where machine resources and power are limited. FPGAs meet such constraints of machine resources and power associated with CNNs. FPGAs have low power consumption, but limited machine resources. Quantization Neural Networks have fewer parameters (bit depth) than CNNs and better estimation accuracy than BNNs.
Although CNNs for regression problems are rarely implemented with FPGAs, our study installed debris pose estimation on an FPGA using the latest edge technology such as quantization neural network. Pose estimations were run on a workstation using 32bit floating-point precision and on an FPGA using 8bit int precision. The average errors were 4.98% and 5.38%, respectively. This demonstrates that the regression problem can be transferred to an FPGA without a significant loss of accuracy. The FPGA power efficiency is more than 218k times that of a workstation implementation.
Although CNNs for regression problems are rarely implemented with FPGAs, our study installed debris pose estimation on an FPGA using the latest edge technology such as quantization neural network. Pose estimations were run on a workstation using 32bit floating-point precision and on an FPGA using 8bit int precision. The average errors were 4.98% and 5.38%, respectively. This demonstrates that the regression problem can be transferred to an FPGA without a significant loss of accuracy. The FPGA power efficiency is more than 218k times that of a workstation implementation.
Event Type
Posters
Research Posters
TimeTuesday, 15 November 20228:30am - 5pm CST
LocationC1-2-3
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