Post-Moore Microelectronics/VLSI Co-Design Postdoctoral Scholar
Lawrence Berkeley National Laboratory
Berkeley, CA 94720
DescriptionBerkeley Lab’s Applied math and Computational Sciences Division (https://crd.lbl.gov/) has an opening for a Postdoctoral Scholar to evaluate and develop devices to hardware/circuit co-design flow for architectural specializations for high performance computing and edge computing applications.
In the absence of Moore’s Law Scaling, the Department of Energy (DOE) must investigate alternative paths to continuing computing performance improvements for scientific applications through architectural specialization. The successful candidate will contribute to the development and evaluation of novel heterogeneous device-based circuit design for extreme heterogeneous SoC (System on Chip) designs, and evaluate their merit for emerging computational workloads for the purpose of maximizing performance and energy efficiency. This work will have
RequirementsWhat is Required:
• PhD or equivalent in a Computing Science or Computer Engineering related scientific discipline.
• Past experience in either Machine learning accelerators or SRAM array design or basic blocks of processor at transistor level.
• Courses or experience in CAD for VLSI algorithms and C++ Programming.
• Proficient in Spice Circuit Simulations, Verilog and hardware design in CMOS, FeFET, NCFET etc.
• Familiarity with hardware EDA/CAD tools and evaluation/modeling tools in order to extend existing infrastructure to rapidly evaluate CMOS designs.
• Demonstrated creativity, initiative and ability to design, develop and implement complex solutions in consultation with designated technical expert(s) and/or supervisor.
• Experience and track-record writing technical papers and reports.
• Experience with the use of script languages and system utilities such as configure, Perl, UNIX shell scripts, and “make.”
• Proven record of working effectively in a team, seeing projects through to completion, meeting deadlines, interacting with users, and thorough documentation of contributions.
• Willingness to learn and develop skills in new topics.
• Previous experience and publications in Processing-In-Memory and Logic-in-Memory architectures is highly desirable.
• Experience with coding in C++/python for CAD tool development for ASIC design.
• Experience with higher-level hardware design languages (HDLs) such as CHISEL, PyMTL, or others.
• Experience with FPGA design flows would also be beneficial.
• Demonstrated ability to lead technical efforts with teams of people will also be beneficial.
Company DescriptionBerkeley Lab is committed to Inclusion, Diversity, Equity and Accountability (IDEA, https://diversity.lbl.gov/ideaberkeleylab/) and strives to continue building community with these shared values and commitments. Berkeley Lab is an Equal Opportunity and Affirmative Action Employer. We heartily welcome applications from women, minorities, veterans, and all who would contribute to the Lab's mission of leading scientific discovery, inclusion, and professionalism. In support of our diverse global community, all qualified applicants will be considered for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, or protected veteran status.