Integration of High-Performance FPGA Chiplets in Heterogenous Systems
DescriptionIn the realm of high-performance heterogeneous computing, closely coupling FPGA accelerators with heterogenous compute elements is a much-needed technology in combating increasing development costs of monolithic solutions. With the development of standardized die-to-die interfaces, this technology is a reality. A new era has begun, chiplets, whereby designers build tiny ICs that contain a well-defined subset of functionality. Designed to be mixed and matched with other chiplets, FPGAs provide the ideal base die to connect all of these small ICs together in one package using standardized high performance die to die interfaces such as Universal Chiplet Interconnect Express (UCIe). This brings the benefits of faster time to market, lower development costs and scalable solutions to increase FPGA functionality. This talk will discuss the “New Era of Chiplets,” and FPGA technology designed specifically to utilize chiplets and standardized interfaces. We examine the robust UCIe open standard and development community that is accelerating HPC to include more customizable, package-level integration, combining best-in-class die-to-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem. We also examine FPGA architecture as a standardized interface, including utilization of a two-dimensional network on chip (2D NoC). Built into the FPGA fabric, the 2D NoC interconnects I/O, memory, internal functional blocks to transfer low latency, high bandwidth data both on chip as well as across die-to-die interfaces. A detailed description of 2D NoC will be included, along with an example of how designers can integrate 2D NoC technology with standard die-to-die interfaces to build high performance heterogeneous computing systems.
Event Type
Exhibitor Forum
TimeThursday, 17 November 20224:30pm - 5pm CST
LocationD171
Recorded
TP
XO/EX