Task Scheduling on FPGA-Based Accelerators without Partial Reconfiguration
DescriptionIn contrast to conventional integrated circuits, Field Programmable Gate Arrays (FPGAs) can be reconfigured dynamically. This flexibility unlocks potential for FPGA-based accelerators to offload tasks in HPC. Scheduling tasks on FPGAs is equivalent to the allocation of chip resources: each offloaded task occupies chip area during its execution. Hence, task scheduling on FPGAs is typically done with Partial Reconfiguration (PR). However, PR requires a high development overhead, requires expert knowledge and has limited portability, making it difficult to apply existing research and lowering the adoption of FPGAs in HPC. We want to aid software developers and vendors to integrate accelerators based on FPGAs without these issues and ask: how we can optimize task scheduling on FPGAs without relying on PR?
We answer this question with three key contributions: first, we introduce an abstraction-agnostic methodology to analyze and compare scheduling strategies for FPGAs. Center of our method is the derivation of scheduling constraints from a machine model representing a target FPGA. The schedules generated for HPC applications are compared for two models. We show that the overhead for avoiding PR is feasible. Second, we propose algorithms to generate recommendations for minimal changes to the program that affect the quality of possible schedules. We show that effective recommendations can be generated for HPC applications. Third, we contribute two polynomial-time scheduling algorithms. Our results can help vendors to provide significantly more streamlined workflows for programming FPGAs, making the platform more appealing and helping the adoption of high-level programming environments like OpenCL for FPGAs.
TimeTuesday, 15 November 20228:30am - 5pm CST