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TZOFFSETTO:-0600
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END:STANDARD
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DTSTAMP:20230124T171525Z
LOCATION:D222
DTSTART;TZID=America/Chicago:20221113T163000
DTEND;TZID=America/Chicago:20221113T170000
UID:submissions.supercomputing.org_SC22_sess436_ws_mchpc105@linklings.com
SUMMARY:Assessing the Memory Wall in Complex Codes
DESCRIPTION:Workshop\n\nAssessing the Memory Wall in Complex Codes\n\nShip
 man, Dominguez-Trujillio, Sheridan, Swaminarayan\n\nMany of Los Alamos Nat
 ional Laboratory's HPC codes are memory bandwidth bound. These codes exhib
 it high levels of sparse memory \naccess which differ significantly from s
 tandard benchmarks. \nIn this paper we present an analysis of the memory a
 ccess of some of our most important code-bases. We then generate micro-ben
 chmarks \nthat preserve the memory access characteristics of our codes usi
 ng two approaches, \none based on statistical sampling of relative memory 
 offsets in a sliding time window at the \nfunction level and another at th
 e loop level. The function level approach is used to   \nassess the impact
  of advanced memory technologies such as LPDDR5 and HBM3 using \nthe gem5 
 simulator. Our simulation results show significant improvements for sparse
  memory access workloads using HBM3 relative to LPDDR5 and better scaling 
 on a per core basis. Assessment of two  different architectures show that 
 higher peak memory bandwidth results in high bandwidth on sparse workloads
 .\n\nSession Format: Recorded\n\nRegistration Category: Workshop Reg Pass
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