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DTSTAMP:20230124T171521Z
LOCATION:C155
DTSTART;TZID=America/Chicago:20221113T153000
DTEND;TZID=America/Chicago:20221113T155300
UID:submissions.supercomputing.org_SC22_sess428_ws_p3hpc114@linklings.com
SUMMARY:Toward Performance Portability of AI Graphs Using SYCL
DESCRIPTION:Workshop\n\nToward Performance Portability of AI Graphs Using 
 SYCL\n\nNarasimhan, El Farouki, Goli, Tanvir, Georgiev...\n\nThe wide adop
 tion of Deep Neural Networks (DNN) has served as an incentive to design an
 d manufacture powerful and specialized hardware technologies, targeting sy
 stems from Edge devices to Cloud and supercomputers.\n\nWhile the proposed
  ONNX as a de facto for AI model description provides the portability of A
 I models across various AI frameworks, supporting DNN models on various ha
 rdware architectures remains challenging.\n\nSYCL provides a C++-based por
 table parallel programming model to target various devices. Thus, enabling
  SYCL backend for an AI framework can lead to a hardware-agnostic model fo
 r heterogeneous systems.\n\nThis paper proposes a SYCL backend for ONNXRun
 time as a possible solution towards the performance portability of deep le
 arning algorithms. The proposed backend uses existing state-of-the-art SYC
 L-DNN and SYCL-BLAS libraries to invoke tuned SYCL kernels for DNN operati
 ons. Our performance evaluation shows that the proposed approach can achie
 ve comparable performance with respect to the state-of-the-art optimized v
 endor-specific libraries.\n\nSession Format: Recorded\n\nTag: Performance 
 Portability\n\nRegistration Category: Workshop Reg Pass
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